Complementary metal oxide silicon (“CMOS”) devices are widely used in various logic circuit applications such as central processing units and memory devices. In many semiconductor device applications, it is important that the semiconductor device exhibit low power consumption, small size and/or high operation speeds. CMOS devices are often capable of meeting all of these requirements. However, as the size of CMOS devices are reduced to very small levels, an effect known as the short channel effect may result as a consequence of the scaling-down of the gate size of the device. This short-channel effect can degrade the performance of the CMOS device.
Conventional CMOS devices are typically fabricated on bulk silicon substrates. However, in such conventional CMOS devices, the characteristics of the device may be strongly influenced by the processing conditions used in fabricating the device when the gate length of the device is scaled down to less than about 50 nm, and conventional CMOS devices may break down completely and cease to operate as semiconductor circuits when the gate length of the device is scaled down to less than about 30 nm. By way of example, certain 30 nm CMOS devices manufactured by Intel Co., Ltd. may exhibit poor current-voltage curve characteristics (I-V characteristics) when compared with conventional CMOS devices.
The use of silicon-on-insulator (“SOI”) semiconductor devices (“SOI devices”) has been suggested as a way of providing CMOS devices with channel lengths of about 30 nm or less that have good I-V characteristics. However, it has been found that fabricating conventional CMOS devices on SOI substrates may result in an increase in the parasitic resistance at the source/drain regions because the silicon layer of the SOI substrate is very thin. As such, a selective epitaxial growth step at the source/drain regions may be included when fabricating transistors in SOI devices. In addition, SOI devices may exhibit relatively poor contact with the substrate such that a floating body effect may arise and/or heat conduction between the device and the substrate may be reduced. All of these effects may act to reduce the performance of the device.
The use of double gate structures (i.e., providing a gate at each side of a channel through which electric current passes) has also been suggested as a way for efficiently reducing the channel length of CMOS devices to less than about 25 nm. Such CMOS devices are known as fin field effect transistors (“fin FET”). Fin FET transistors may provide improved gate control characteristics, which may result in reduced leakage current between the source and drain when compared with a conventional, single gate CMOS device, thereby improving the drain-induced barrier lowering (DIBL) phenomenon. In addition, the threshold voltage of a fin FET device may be varied dynamically because of the double gate. As such, the switching characteristic of the channel in the transistor may be improved as compared to conventional single gate CMOS devices. Accordingly, the driving current of the transistor may be increased and the short channel effect may be reduced or prevented.
However, one potential disadvantage of fin FET devices is that they may exhibit increased parasitic resistance in the source/drains. This effect may occur because the width of the fin in the fin FET may be on the order of a few nanometers, and thus the pad contact area in which electrical contact is made with the source/drain regions may be significantly smaller than the contact area in conventional CMOS devices. Accordingly, the parasitic resistance may be increased at the pad/n-junction, thereby reducing the driving current of the fin FET.
One way of reducing the parasitic resistance in fin FET transistors that has been suggested is to deposit polycrystalline silicon or silicon germanium (SiGe) on the source/drain regions, as disclosed in the article entitled “Quasi-Planar fin FETs with selectively grown germanium raised source/drain”, IEEE International SOI Conference, October 2001, that is incorporated herein by reference. As noted above, the source/drain regions in conventional fin FETs are thin and may exhibit a relatively high electrical resistance; thus the driving current of these devices may be significantly deteriorated as compared to conventional, single gate devices. According to the above-referenced IEEE International SOI Conference article, a germanium layer may be formed on the source/drain regions of the fin FET using a selective epitaxial growth process in order to enlarge the contact surface of the source/drain regions with which a contact pad may make electrical contact. This enlargement of the contact surface may act to reduce the electrical resistance at the source/drain regions.
Another solution to the problem of increased parasitic resistance in the fin FET that has been suggested is covering the entire source/drain region with raised source/drain silicon (RSD Si) to enlarge the contact surface of the source/drain region, as disclosed in the article entitled “Extension and source/drain design for high-performance fin FETs devices”, IEEE Transactions on Electron Devices, Vol. 50, No. 4, April 2003, the contents of which are incorporated herein by reference. However, the enlarged contact surface provided by the use of RSD Si may require that the gate be about two times as tall as the height of the source/drain in the fin FET. An over-etching process is also required for removing the spacer formed on the source/drain regions.